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Lizely

Logic Gate Puzzle

Wire real directed AND, OR, and NOT graphs through five fixed levels and make every final output TRUE.

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How to use

  1. 1.Select a SOURCE or gate OUT port, then choose an empty gate or final OUTPUT IN port to create a directed wire.
  2. 2.Fill every gate input and route every gate toward OUTPUT; click a filled IN with no OUT selected to disconnect and revise it.
  3. 3.Make the complete circuit evaluate to TRUE in all five fixed levels for exactly 1,000 points.

About Logic Gate Puzzle

Logic Gate Puzzle is a five-level directed-circuit game built around three fundamental digital operations: AND, OR, and NOT. Each board gives you fixed binary sources, one or more gate cards, and a final OUTPUT card. Your task is not to answer a multiple-choice question. You must construct an actual directed graph by wiring output ports to input ports until the complete circuit evaluates to TRUE.

Every connection follows a visible OUT-to-IN rule. Select an OUT port on a source or gate, then select an empty IN port on a gate or the final OUTPUT. One output may fan out to more than one destination, which is essential in the opening AND level. Each input accepts exactly one driver. Clicking a filled input while no output is selected disconnects that wire, so a recoverable wrong circuit can be edited without restarting.

The first level introduces an AND gate with one TRUE source and one FALSE distractor. AND returns TRUE only when both of its inputs are TRUE, so the useful source must fan out to both input ports. The second level introduces OR, which returns TRUE when either input is TRUE. Its three sources encourage you to route one TRUE signal while still filling both required gate ports.

The third level focuses on NOT. An inverter has one input and produces its opposite, so a FALSE source becomes TRUE. Later levels combine gates: one circuit inverts a FALSE source before joining it with a TRUE source through AND, while the final circuit feeds an OR branch and a NOT branch into a last AND gate. These are original fixed puzzles rather than generated exercises.

A graph is evaluated only when every declared gate input and the final OUTPUT input have exactly one incoming wire. Every gate output must also have a directed path to the final output. Partial diagrams remain editable and do not count as mistakes. Unknown ports, input-to-input attempts, output-to-output attempts, self-links, a second driver for an occupied input, duplicate edges, and directed cycles are rejected without changing the board.

The evaluation engine resolves the graph from the final OUTPUT backward through its drivers. Source nodes provide fixed Boolean values. AND requires two inputs and returns true only when both are true. OR requires two inputs and returns true when either is true. NOT requires exactly one input and reverses it. The game never guesses a value for a missing port and never evaluates a cyclic graph.

Completing a graph with TRUE at the final output solves the level for exactly 200 points. Five solved circuits therefore produce an exact perfect score of 1,000. There is no timer, speed bonus, random source value, hidden multiplier, adaptive difficulty, or partial-credit formula. Restart always returns to the same first board with empty wires and zero score.

A complete FALSE circuit records one recoverable graph error. Disconnect a wire and try another valid topology. Rebuilding exactly the same wrong edge set is deduplicated, so it cannot consume another error. A second distinct complete graph that also produces FALSE closes the run. Structural rejections do not count as logical errors because they never enter the graph.

Pointer and touch players use large source, gate, input, and output buttons. Keyboard play uses Tab to move through every port and Enter or Space to select an output, connect an input, or disconnect an occupied input. The selected output is visually and textually identified, every connected input names its driver, and a directed wire ledger lists each edge as FROM to TO.

The independent test does more than replay the product data. It restates all ten externally sourced truth-table rows: four for AND, four for OR, and two for NOT. It also defines five literal solution graphs, executes the full 200-to-1,000 route, proves fan-out, checks complete-graph evaluation, rejects occupied input ports and a real directed cycle, rebuilds an identical wrong graph, creates a second distinct FALSE graph, and verifies terminal freeze and deterministic restart.

Truth-table behavior is documented by two accessible electronics references linked below. The level names, source arrangements, graph layouts, scoring, deduplication rule, and interface are original Lizely game content. This page makes no claim to simulate transistor timing, voltage thresholds, propagation delay, electrical loading, or physical hardware. It is a Boolean graph puzzle for entertainment and introductory practice.

Everything runs locally in the browser. There is no account requirement, download, upload, API, remote solver, model, external asset, random service, or personal data. Only the shared best completed score may remain in this browser. Double-press Escape for the simulated spreadsheet boss screen, then repeat the shortcut to return to the unchanged circuit. Related games offer different connection and deduction challenges without replacing this directed logic-gate workflow.

Methodology & sources

Each level declares immutable SOURCE, AND, OR, NOT, and OUTPUT nodes. OUT ports may fan out; each IN accepts one driver. Connection validation rejects malformed directions, self-links, occupied inputs, duplicates, and cycles. A complete graph fills all inputs and requires every gate to reach OUTPUT, then recursively applies the sourced truth tables. TRUE advances for 200; sorted edge signatures deduplicate FALSE graphs; two distinct FALSE graphs deadlock.

Frequently asked questions

How do I play Logic Gate Puzzle?
Connect OUT ports to IN ports until every gate is complete and the final OUTPUT is TRUE. Tab plus Enter or Space provides a complete keyboard route.
What do AND, OR, and NOT do?
AND is true only when both inputs are true, OR is true when either input is true, and NOT reverses its single input.
Do invalid wires count as mistakes?
No. Cycles, duplicate drivers, malformed directions, and unknown ports are rejected atomically. Only a complete valid graph whose output is FALSE records an error.

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