The Fibonacci sequence is the integer series 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, and so on, defined by the seeds F(0) = 0 and F(1) = 1 with the recurrence F(n) = F(n − 1) + F(n − 2) for n ≥ 2, the standard zero-based form recorded by the NIST Digital Library of Mathematical Functions and by OEIS A000045. A Fibonacci number generator using Verilog code is often paired with a separate browser-based reference so the hardware output can be checked against an independently produced exact list. The Fibonacci Sequence Generator is that kind of reference: type a count from 1 through 1,000, click generate, and receive every value from F(0) to the final requested index as one indexed line per term. Because each value is held as a BigInt and converted directly to decimal text, the output keeps every digit exact even past the point where ordinary JavaScript numbers collapse into rounding. The whole pipeline runs in the current page, so nothing about the chosen count or the produced digits leaves the browser.
What the Fibonacci Sequence Is and How It Is Defined
Most textbook worksheets display the list starting at 1, 1 because they skip the zero seed, but that convention mismatch is one of the most common sources of off-by-one errors in Verilog testbenches. The generator sticks to the zero-based definition recorded by OEIS A000045, so F(0) always equals 0, F(1) always equals 1, and every later term is the sum of the two preceding terms. That form also lines up neatly with the way hardware description languages count registers, since a Verilog reg [WIDTH-1:0] fib indexing into a memory block typically starts at zero as well.
For a wider walkthrough of why the zero-based form is the safer choice when HDL code indexes start at 0, the concept of Fibonacci sequence explained from F(0) onward guide covers the same definition with extra worked examples.
Once the recurrence is locked to that form, a few concrete values become trustworthy reference points for any Verilog implementation:
| Index n | F(n) | Use as a Verilog sanity check |
|---|---|---|
| 0 | 0 | Seed: first value the hardware should ever emit |
| 1 | 1 | Second seed; confirms F(0) was not skipped by the FSM |
| 2 | 1 | First true recurrence; sum of F(1) and F(0) |
| 5 | 5 | Catches the duplicate 1 values from F(1) and F(2) |
| 10 | 55 | Common textbook example used in many FPGA lab exercises |
| 20 | 6765 | Fits comfortably inside a 32-bit register |
| 46 | 1836311903 | Last value representable in a signed 32-bit register |
Every entry in that table is one addition away from a Verilog implementation, which makes it the cheapest baseline for a sanity test before any wider simulation is started.
Why Verilog and HDL Developers Need an Exact Reference
Hardware description languages handle integer overflow silently. A Verilog register of width 32 will wrap modulo 2^32 the moment a Fibonacci value crosses 2^31 − 1, and a testbench that only prints the low 32 bits will look correct even when the upper half is garbage. The same is true for SystemVerilog, VHDL unsigned, and any C test harness that uses uint32_t. Against that backdrop, the value of a reference list depends less on its shape and more on its precision: every digit in the expected sequence has to be exact, regardless of where it sits in the run.
The fastest way to get that exact list is to ask a tool that does not need to approximate at all. The Fibonacci Sequence Generator stores each term as a BigInt, runs one addition per requested index, and writes the result as plain decimal text. There is no closed-form golden-ratio shortcut, no floating-point square root, and no silent rounding when the term count climbs past F(78).
For anyone implementing the recurrence in a wider numeric workflow, a similar window-based shortcut is available in generate random numbers in MATLAB without code. The general idea — let the tool produce the exact numeric reference so your code only has to match it — carries over.
Generate an Indexed Fibonacci Reference List
The interface is intentionally small. Three steps cover every supported use case from a quick sanity check to a full thousand-term fixture for a deep testbench.
- Enter a whole-number term count from 1 through 1,000 in the input box. The count always counts F(0) as the first term, so entering 1 returns only F(0), entering 20 returns F(0) through F(19), and entering 1000 returns F(0) through F(999).
- Click the generate button and wait for the indexed list to appear. The summary above the list always states the count you entered and the final index that was produced, so a quick glance confirms whether the run matches the depth your Verilog testbench is configured for.
- Copy the newline-separated text with the copy button, or select the visible text manually if clipboard permission is unavailable. Each line keeps its index, so the position of a term stays unambiguous even near the start where 0, 1, 1, 2 would otherwise collide visually.
Reading the Output: Indexed Lines, Not Raw Numbers
Each line of the output is formatted as F(index) = decimal value. The index is the zero-based position, and the value is the exact decimal representation of that Fibonacci number with no thousands separators and no scientific notation. That format is what makes the output safe to paste into a Verilog comment block, a C header, or a Markdown table — the index travels with the digit, so a misplaced term cannot be mistaken for its neighbour.
Editing the term count clears the previous run. This matters in a hardware workflow where the test fixture is usually regenerated for each new depth: there is no chance of an older sequence lingering under a fresh input that has not yet been processed. The summary panel updates only after the new run completes, so the on-screen result always matches the count shown above it.
For values that comfortably fit inside 32 bits, the output is short and readable. The 20-term list spans F(0) = 0 through F(19) = 4181 and fits inside a single screen. The 50-term list reaches F(49) = 7778742049, and the digits keep adding without compression past that point, which is exactly the behaviour you want when comparing against a Verilog implementation that uses arbitrary-width registers.
BigInt Precision Past the 32-Bit Boundary
JavaScript Number values can represent integers exactly only up to 2^53 − 1, and the Fibonacci sequence crosses that safe-integer boundary surprisingly early: F(78) = 8944394323791464 still fits inside Number.MAX_SAFE_INTEGER, while F(79) = 14472334024676221 and F(80) = 23416728348467685 already exceed it. From that index onward, any tool that stores values as floating-point doubles will start dropping the lowest digits and printing approximations — the printed number may still look plausible, but the last few digits will silently change whenever the term count grows.
The generator sidesteps the entire issue by holding each term in a BigInt and converting to decimal text only when the row is written. F(100), for example, appears as the exact 21-digit number 354224848179261915075 rather than as 3.5422484817926193e+20 or any other compressed form. The same approach keeps F(500) — a 105-digit integer — accurate to every digit, which is also why the one thousand-term ceiling exists: at that depth, F(999) carries hundreds of digits, and the indexed output is large enough to require scrolling through hundreds of lines.
Input Rules: What Counts and What Gets Rejected
The input is a plain base-ten term count, not a target value and not a final index. Entering 100 does not return F(100) — it returns the first 100 rows from F(0) through F(99). The summary panel always restates the final index that was produced, so a misread cannot slip through unnoticed. A request for one term returns only F(0); a request for twenty terms returns F(0) through F(19).
Decimals, scientific notation, signs, thousands separators, negative counts, and empty input are all rejected rather than rounded. Counts above 1000 are also rejected; the upper bound is a product performance limit on the rendered and copied text, not a mathematical limit on the Fibonacci sequence. For longer runs, a dedicated programming environment with a specialised arbitrary-precision library is the appropriate next step.
A few practical checks worth running before you copy a generated run into a Verilog project: confirm the final index printed in the summary matches the depth your testbench expects, confirm the count equals the final index plus one, and scan the early rows to confirm the run really starts at F(0) = 0. Those three checks catch almost every accidental misuse of the tool.
Using the Output as Verilog Testbench Data
The most direct use is as a golden reference in a testbench. Because each line carries its index, you can paste the output into a $display or $strobe format string such as $display("F(%0d) = %s", expected_idx, expected_val); and compare directly against the value your hardware produces. Repeating this for a few hard indices — say F(45), F(78), and F(100) — exercises the 32-bit overflow transition, the safe-integer crossover, and a comfortably multi-word result in a single short test, without needing to enumerate every index in between.
For larger fixtures, the indexed list also works as a comment block at the top of a test file. Anyone reading the file later can see the exact sequence the testbench is asserting, without running the simulation. That visibility tends to catch mistakes earlier than the simulation itself does, particularly in cross-team review where the verifier and the implementer are different people.
Finally, the output behaves well as a quick reference while you write the Verilog recurrence itself. Adding two wide Fibonacci registers in SystemVerilog is a familiar pattern, and the generator provides the expected values for any sample N you choose — up to F(999) — without leaving the page or trusting a calculator that quietly rounds its last few digits.